In the current DRAM design, boosted voltages are used to turn the wordline on and off. The value of these voltages creates a tradeoff between performance and standby current consumption due to the gate induced drain leakage (GIDL) at the large number of wordline drivers (e.g., see FIGS. 1(a)-1(b), vpp and vnwl are the positive and negative wordline voltages respectively). In FIG. 1(a), the pre-driver is used to drive the DRAM cell (as shown in FIG. 1(c)) via the bwordline and wordline. Please refer to FIG. 1(d), Vt(V) varies according to the temperature and the process involved. For example, the Vt(V) under a high temperature and/or a fast process is relatively low and Vt(V) under a low temperature and/or a slow process is relatively high. The positive wordline voltage “vpp” must be set high enough for the memory cell as shown in FIG. 1(c) to function at worst case condition. This voltage margin leads to approximately 200 mV of overkill for conditions where the array threshold voltage Vt(V) is nominal or low (see FIG. 1(d)). For this condition, we are unnecessarily increasing standby current consumption. Using the case of 64K wordline pre-drivers on 8bank as an example, GIDL becomes non-negligible, and must be compensated.
In previous methods, only fixed positive and negative wordline voltage values are used. The positive and negative wordline voltage values are not changed to compensate for Vt(V) of the array device. FIG. 2(a) is a schematic circuit diagram of a conventional DRAM positive wordline voltage compensation device. In FIG. 2(a), the limiter is a comparator receiving a vpp feedback signal and a PVT (Vt(V)) insensitive reference and generating a first enable signal en, OSC is an oscillator receiving the first enable signal en and generating an oscillating signal when the first enable signal en is active (i.e. when the vpp feedback signal is less than the PVT insensitive reference), and the charge pump receives a second enable signal en and the oscillating signal and raises the vpp to a fixed level as shown in FIG. 2(b).
Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the applicant finally conceived a DRAM positive wordline voltage compensation device for array device threshold voltage and a voltage compensating method thereof.